Performance Analysis of SRAM Design using Variable Body Bias Technique

Authors:D VAMSI KRISHNA, C K MEGHALATHA

0559-0563

A Novel Approach for Fully Reused VLSI Architecture of FM0/Manchester Encoding using Sols Technique for DSRC Applications

Authors:M. VENU, G. LAXMI PRASANNA, B. NAGARJUN SINGH

0564-0569

Design of A High Speed Architecture for DDR SDRAM Controller Interfaced with AHB

Authors:VADLA SIDDIRAMULU, B. KIRAN KUMAR

0570-0575

Enhancement of MRI Images Based On Super-Resolution Reconstruction for Cardiac MRI Using Coupled Dictionary Learning

Authors:M. VENU, SK. INTHIYAZ ALI, B. NAGARJUN SINGH

0576-0580

CORDIC Designs for Fixed Angle of Rotation

Authors:B. THIRUPATHI, L. R. SIVA

0581-0587

Reconfigurable Test Architecture for Concurrent Fault Detection using SRAM Cells

Authors:K. SRAVANI, S. PARVEEN

0588-0591

Implementation High-Level Syntax Architecture for Efficient Integer DCT for HEVC

Authors:M. VENU, MIRZA JASEEM RUKHSAR, B. NAGARJUN SINGH

0592-0597

Design of High Performance 64-Bit MAC

Authors:MEDI SWATHI, M. VENKATESHWARLU

0598-0602

A Novel Full Comparator Design using Quantum-Dot Cellular Automata

Authors:K. LAKSHMIDEVI, P. DEEPTHI JORDHANA

0603-0608

Design and Implementation of an On Chip Permutation Network for Multiprocessor System on Chip

Authors:KATTUBADDI MADHURI, M. VENKATESHWARLU

0609-0615